1. Field of the Invention
The present invention relates to an SR flip-flop.
2. Description of the Related Art
In digital circuits, SR flip-flops are widely employed. The SR flip-flop includes a set terminal and a reset terminal, and outputs, via an output terminal, an output signal that corresponds to a set signal and a reset signal respectively input via the set terminal and the reset terminal. When the set signal is asserted (switched to the high-level state, for example), the SR flip-flop switches the output signal to a first level (e.g., high level) at a positive edge timing of the set signal. When the reset signal is asserted, the SR flip-flop switches the output signal to a second level (e.g., low level) at a positive edge timing of the reset signal.
In general, examples of such an SR flip-flop include a NOR SR flip-flop including two cross-coupled NOR (negative OR) gates, and a NAND SR flip-flop including two cross-coupled NAND (negative AND) gates.
Such a NAND SR flip-flop and such a NOR SR flip-flop are configured on the assumption that the signal levels (amplitude levels) of the set signal and the reset signal thus input (which will be collectively referred to as “input signals”) are equal to the signal level of the output signal thereof.